ButterflyMP3

vs1001.h

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00001 
00028 /* 
00029  * Modified for ButerflyMP3 13/07/2004  
00030  */
00031 #ifndef __VS1001_H
00032 #define __VS1001_H
00033 
00034 #define DREQ_DDR        DDRE
00035 #define BSYNC_DDR       DDRE    
00036 #define xDCS_DDR        DDRE 
00037 #define MP3_DDR         DDRB
00038 #define RESET_DDR       DDRB
00039 
00040 #define DREQ_PORT       PINE
00041 #define BSYNC_PORT      PORTE    
00042 #define xDCS_PORT       PORTE    
00043 #define MP3_PORT        PORTB
00044 #define RESET_PORT      PORTB
00045 
00046 #define DREQ_PIN        PE6                             // DREQ signal
00047 #define BSYNC_PIN       PE5                             // BSYNC signal
00048 #define xDCS_PIN        PE5                             // xDCS signal (new mode)
00049 #define MP3_PIN         PB0                             // MP3 control bit
00050 #define RESET_PIN       PB5                             // -RESET signal
00051 
00052 //TODO: add code to use SCI_STATUS to determine 
00053 
00054 //#define VS1000_NEW                                    // Use the new mode for VS1053 and newer
00055 //#define VS1001
00056 #define VS1011
00057 //#define VS1053
00058 
00059 
00060 // defines for Mode control of vs1001k
00061 #ifdef VS1001
00062 #define SM_DIFF         1
00063 #define SM_FFWD         2
00064 #define SM_RESET        4
00065 #define SM_MP12         8
00066 #define SM_PDOWN        16
00067 #define SM_DAC          32
00068 #define SM_DACMONO      64
00069 #define SM_BASS         128
00070 #define SM_DACT         256
00071 #define SM_IBMODE       512
00072 #define SM_IBCLK        1024
00073 #endif
00074 
00075 #ifdef VS1011            //Bit  Function Value Description 
00076 #define SM_DIFF         (1<<0)  //  Differential 0 normal in-phase audio 1 left channel inverted 
00077 #define SM_LAYER12      (1<<1)  //  Allow MPEG layers I & II 0 no 1 yes 
00078 #define SM_RESET        (1<<2)  //  Soft reset 0 no reset 1 reset 
00079 #define SM_OUTOFWAV     (1<<3)  //  Jump out of WAV decoding 0 no 1 yes 
00080 #define SM_SETTOZERO1   (1<<4)  //  set to zero 0 right 1 wrong 
00081 #define SM_TESTS        (1<<5)  //  Allow SDI tests 0 not allowed 1 allowed 
00082 #define SM_STREAM       (1<<6)  //  Stream mode 0 no 1 yes 
00083 #define SM_SETTOZERO2   (1<<7)  //  set to zero 0 right 1 wrong 
00084 #define SM_DACT         (1<<8)  //  DCLK active edge 0 rising 1 falling 
00085 #define SM_SDIORD       (1<<9)  //  SDI  bit order 0 MSb first 1 MSb last 
00086 #define SM_SDISHARE     (1<<10) //  Share SPI chip select 0 no 1 yes 
00087 #define SM_SDINEW       (1<<11) //  VS1002 native SPI modes 0 no 1 yes 
00088 #define SM_SETTOZERO3   (1<<12) //  set to zero 0 right 1 wrong 
00089 #define SM_SETTOZERO4   (1<<13) //  set to zero 0 right 1 wrong 
00090 #endif 
00091 
00092 #ifdef VS1053            //Bit  Function Value Description 
00093 #define SM_DIFF         (1<<0)  //  Differential 0 normal in-phase audio 1 left channel inverted 
00094 #define SM_LAYER12      (1<<1)  //  Allow MPEG layers I & II 0 no 1 yes 
00095 #define SM_RESET        (1<<2)  //  Soft reset 0 no reset 1 reset 
00096 #define SM_CANCEL       (1<<3)  //  Cancel decoding current file 0 no 1 yes 
00097 #define SM_EARSPEAKER_LO (1<<4) //  EarSpeaker low setting  0 off 1 active 
00098 #define SM_TESTS        (1<<5)  //  Allow SDI tests 0 not allowed 1 allowed 
00099 #define SM_STREAM       (1<<6)  //  Stream mode 0 no 1 yes 
00100 #define SM_EARSPEAKER_HI (1<<7) //  EarSpeaker high setting  0 off 1 active 
00101 #define SM_DACT         (1<<8)  //  DCLK active edge 0 rising 1 falling 
00102 #define SM_SDIORD       (1<<9)  //  SDI  bit order 0 MSb first 1 MSb last 
00103 #define SM_SDISHARE     (1<<10) //  Share SPI chip select 0 no 1 yes 
00104 #define SM_SDINEW       (1<<11) //  VS1002 native SPI modes 0 no 1 yes 
00105 #define SM_ADPCM        (1<<12) //  ADPCM recording active 0 no 1 yes 
00106 #define SM_LINE1        (1<<14) //  MIC / LINE1 selector 0 MICP 1 LINE1
00107 #define SM_CLK_RANGE    (1<<15) //  Input clock range 0 12..13 MHz 
00108 #endif
00109 
00110 // defines for SCI registers
00111 #ifdef VS1001
00112 #define SCI_MODE                0
00113 #define SCI_STATUS              1
00114 #define SCI_INT_FCTLH   2
00115 #define SCI_CLOCKF              3
00116 #define SCI_DECODE_TIME 4
00117 #define SCI_AUDATA              5
00118 #define SCI_WRAM                6
00119 #define SCI_WRAMADDR    7
00120 #define SCI_HDAT0               8
00121 #define SCI_HDAT1               9
00122 #define SCI_AIADDR              10
00123 #define SCI_VOL                 11
00124 #endif
00125 
00126 #if defined (VS1011) || defined (VS1053)
00127 //                      Reg           Type Reset Time1    Description 
00128 #define SCI_MODE        0x0         // rw  0     70 CLKI4 Mode control 
00129 #define SCI_STATUS      0x1         // rw  0x2C3 40 CLKI  Status of VS1011e 
00130 #define SCI_BASS        0x2         // rw  0   2100 CLKI  Built-in bass/treble enhancer 
00131 #define SCI_CLOCKF      0x3         // rw  0     80 XTALI Clock freq + multiplier 
00132 #define SCI_DECODE_TIME 0x4         // rw  0     40 CLKI  Decode time in seconds 
00133 #define SCI_AUDATA      0x5         // rw  0   3200 CLKI  Misc. audio data 
00134 #define SCI_WRAM        0x6         // rw  0     80 CLKI  RAM write/read 
00135 #define SCI_WRAMADDR    0x7         // rw  0     80 CLKI  Base address for RAM write/read 
00136 #define SCI_HDAT0       0x8         // r   0       -      Stream header data 0 
00137 #define SCI_HDAT1       0x9         // r   0       -      Stream header data 1 
00138 #define SCI_AIADDR      0xA         // rw  0   3200 CLKI2 Start address of application 
00139 #define SCI_VOL         0xB         // rw  0   2100 CLKI  Volume control 
00140 #define SCI_AICTRL0     0xC         // rw  0     50 CLKI2 Application control register 0 
00141 #define SCI_AICTRL1     0xD         // rw  0     50 CLKI2 Application control register 1 
00142 #define SCI_AICTRL2     0xE         // rw  0     50 CLKI2 Application control register 2 
00143 #define SCI_AICTRL3     0xF         // rw  0     50 CLKI2 Application control register 3
00144 #endif 
00145 
00146 typedef enum {
00147         SOFT_RESET,
00148         HARD_RESET
00149 } reset_e;
00150 
00151 
00152 
00153 // setup I/O pins and directions for
00154 // communicating with the VS1001
00155 void vs1001_init_io(void);
00156 
00157 // setup the VS1001 chip for decoding
00158 void vs1001_init_chip(void);
00159 
00160 // reset the VS1001
00161 void vs1001_reset(reset_e r);
00162 
00163 // send a number of zero's to the VS1001
00164 void vs1001_nulls(unsigned int nNulls);
00165 
00166 void vs1001_read(uint8 address, uint16 count, uint16 *pData);
00167 
00168 //
00169 // write one or more word(s) to the VS1001 Control registers
00170 //
00171 void vs1001_write(uint8 address, uint16 count, uint16 *pData);
00172 
00173 void vs_1001_setvolume(unsigned char left, unsigned char right);
00174 
00175 // send MP3 data
00176 inline void vs1001_send_data(unsigned char b);
00177 inline void vs1001_send_32(unsigned char *p);
00178 
00179 // test with beeps
00180 void vs1001_sine_test(void);
00181 
00182 
00183 #endif
00184 
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